Superconducting Transmission-Line Guideline and Calculator

Overview

This page provides a combined design guideline, formula reference, and interactive calculator for superconducting transmission lines used in AQFP, SFQ, and related superconducting digital circuits.

The calculator implements a Chang-type closed-form analytical model that estimates per-unit-length inductance, capacitance, characteristic impedance, propagation velocity, and delay for a superconducting stripline or microstrip-like wiring layer. It is intended for:

• Early-stage design — quickly estimating line parameters before layout
• Layer-stack comparison — comparing BAS, COU, CTL, or custom layer definitions
• Student training — understanding how geometry, penetration depth, and dielectric properties interact
• Approximate delay / impedance budgeting — e.g., checking whether a long control line adds unacceptable delay

What this tool is for

First-order analytical estimation for design exploration and education.

What this tool is NOT

A replacement for field-solver-based EM extraction. For final layout sign-off, always use an EM simulator (e.g. Sonnet, FastHenry, or the extraction step in your process PDK).

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When to Use This Tool

Use case	Appropriate?
Quick impedance estimate for a new layer	✅ Yes
Comparing two wiring options at early design stage	✅ Yes
Rough delay budget for a long control line	✅ Yes
Sign-off extraction for tapeout	❌ No — use EM solver
Coupled-line / differential-pair analysis	❌ No — single-line model only
Lossy or high-frequency (> 100 GHz) behavior	❌ No — TEM model only

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Physical Meaning of the Parameters

Geometry parameters

  ┌──────────────────────┐  ← upper conductor (width W, thickness t₁, λ₁)
  └──────────────────────┘
  ╔══════════════════════╗  ← dielectric (height h, relative permittivity εᵣ)
  ╚══════════════════════╝
  ┌──────────────────────┐  ← ground plane (thickness t₂, λ₂)
  └──────────────────────┘

Symbol	Meaning	Typical range
W	Line width	1–10 μm
h	Dielectric thickness between line and ground plane	0.1–2 μm
t₁	Upper conductor (signal line) thickness	0.1–0.5 μm
t₂	Ground-plane thickness	0.2–0.5 μm
λ₁	London penetration depth of upper conductor	≈ 0.08–0.25 μm (NbN, Nb, Al)
λ₂	London penetration depth of ground plane	≈ 0.08–0.25 μm
εᵣ	Relative dielectric constant of insulator	≈ 4.0 (SiO₂), ≈ 9.8 (Si₃N₄)

Why the London penetration depth matters

In ordinary (non-superconducting) microstrip, the magnetic field is excluded from the metal surfaces immediately. In a superconductor, the magnetic field actually penetrates a short distance λ into the conductor — the London penetration depth.

This extra field penetration adds an additional inductive contribution beyond the geometric (dielectric-space) term:

$$L=\frac{{\mu }_0}{W\cdot K}[h+{\lambda }_1\coth \left(\frac{t_1}{{\lambda }_1}\right)+{\lambda }_2\coth \left(\frac{t_2}{{\lambda }_2}\right)]$$

For very thick conductors (t/λ >> 1), coth(t/λ) → 1 and the penetration term reduces to simply λ. For thin films (t/λ ~ 1), coth(t/λ) is appreciably larger than 1, meaning the inductance increases noticeably.

Consequence for design: ground planes or signal layers that are only a few times thicker than λ will increase the line inductance. For typical Nb-based processes with λ ≈ 80 nm and t ≈ 300–500 nm, t/λ ≈ 3.75–6.25, so coth(t/λ) ≈ 1.001–1.000. The penetration correction is small but non-zero in this regime, and it becomes significant for processes with larger λ (e.g., NbN or AlN-barrier junctions).

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Interactive Calculator

This calculator estimates the per-unit-length inductance and capacitance of superconducting transmission lines using a Chang-type analytical model. It includes a fringing-field correction factor K that accounts for finite conductor thickness and provides reasonable accuracy even for moderately narrow lines (W/h ≥ 1).

The calculator is meant to be read together with the model notes and source literature below, not used as a black-box numerical widget.

Process & Line Preset

Process:Chang Spreadsheet Default

Line type:

BAS — Base-layer stripline

Geometry

W — line width

μm

l — line length

μm

h — dielectric thickness

μm

t₁ — upper conductor thickness

μm

t₂ — ground-plane thickness

μm

Material Parameters

εᵣ — relative dielectric constant

—

λ₁ — London depth, upper conductor

μm

λ₂ — London depth, ground plane

μm

Use effective dielectric constant εᵣₑ (for microstrip-like lines)

Model Options

Corrected Chang formula — uses t₂ in ground-plane penetration term: λ₂ · coth(t₂/λ₂)Legacy Excel mode — uses h in ground-plane penetration term: λ₂ · coth(h/λ₂)matches original spreadsheet output

The original spreadsheet uses h rather than t₂ in the lower-conductor penetration term. For the provided default parameters the numerical difference is very small (BAS: no difference because h = t₂; COU: L increases by ≈ 0.010 % when corrected; CTL: ≈ 0.007 %). The corrected model is recommended for new process definitions where t₂ ≠ h.

Results

K (Chang geometry factor)1.245—

εᵣₑ (effective dielectric)4.0000—

L — inductance / length0.09679pH/μm

C — capacitance / length0.7055fF/μm

Z₀ — characteristic impedance11.71Ω

v — propagation velocity1.21e+8m/s

Total L (for l = 5 μm)0.4840pH

Total C (for l = 5 μm)0.003527pF

Total propagation delay0.04132ps

Delay per unit length0.008264ps/μm

Delay per 40 μm0.3305ps/40 μm

Model Validity

W/h = 16.0W/t₁ = 16.0W/λ₁ = 60.0t₂/λ₂ = 3.75

HIGH High — wide-line conditions satisfied; analytical result is expected to be reliable.

High: W/h ≥ 10, W/t₁ ≥ 10, W/λ₁ ≥ 10 — wide-line approximation is likely reasonable.

Medium: W/h ≥ 1 but one or more conditions not met — first-order estimate, field-solver validation recommended.

Low: W/h < 1 — outside the preferred range of the analytical model.

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Formula Summary

1. Chang Geometry Factor K

The factor K accounts for the fringing fields at the edges of the conductor. For a physical conductor of finite width W and thickness t₁ above a ground plane at distance h, the electromagnetic field spreads slightly beyond the geometric width. This effectively widens the conductor to W·K, increasing capacitance and decreasing inductance relative to a zero-thickness parallel-plate approximation.

$$K=\frac{W+2\mathrm{\Delta }}{W}=1+\frac{a_{c}h}{W}\tanh \left(b_c\frac{t_1}{h}\right)$$

Reference

Primary model: W. H. Chang, “The inductance of a superconducting strip transmission line”, Journal of Applied Physics 50(12), 8129-8134, 1979. This is the main analytical reference behind the stripline inductance model used here. Chang's paper explicitly treats finite-width superconducting strip transmission lines and reports good accuracy when W/h is larger than approximately unity.

where $a_c=4.226$ and $b_c=1.64$ are constants calibrated against the original Chang spreadsheet (see Notes on the Original Spreadsheet).

Intermediate geometry variables computed during K evaluation:

Variable	Formula	Description
W/h	W/h	Aspect ratio
t₁/h	t₁/h	Conductor thickness ratio
β	1 + t₁/h	Effective height ratio
p	(W/h) / β	Reduced width
Δ	(a_c/2)·h·tanh(b_c·t₁/h)	Per-edge fringing width
K	(W + 2Δ)/W	Effective width ratio

2. Inductance per Unit Length

Full Chang expression (recommended):

$$L=\frac{{\mu }_0}{W\cdot K}\{h+{\lambda }_1[\coth \left(\frac{t_1}{{\lambda }_1}\right)+\frac{r_b}{2p}\text{csch}\left(\frac{t_1}{{\lambda }_1}\right)]+{\lambda }_2\coth \left(\frac{t_2}{{\lambda }_2}\right)\}$$

Reference

Model scope: Chang's 1979 stripline expression is the right first-order model for a single finite-width superconducting line over a reference plane. Once the routing geometry stops looking like that idealized cross-section, move to extraction-based tools and measured-process data instead of extending the closed form too far.

Wide-line approximation (csch term → 0 when t₁/λ₁ >> 1):

$$L\simeq \frac{{\mu }_0}{W\cdot K}[h+{\lambda }_1\coth \left(\frac{t_1}{{\lambda }_1}\right)+{\lambda }_2\coth \left(\frac{t_2}{{\lambda }_2}\right)]$$

For the default parameters (t₁/λ₁ ≈ 3.75–6.25), the difference between the full and wide-line expressions is less than 0.1 %.

3. Capacitance per Unit Length

$$C=\frac{{\epsilon }_0{\epsilon }_{re}}{h}\cdot W\cdot K$$

Note the symmetry: K appears in the numerator of C and the denominator of L, so it simultaneously increases capacitance and decreases inductance.

4. Effective Dielectric Constant (for CTL / microstrip-like lines)

For stripline-like layers (signal conductor sandwiched between two ground planes), ${\epsilon }_{re}={\epsilon }_r$.

For microstrip-like control lines (CTL), where the field extends partly into air, an effective dielectric constant is used. The Hammerstad & Jensen quasi-TEM formula is:

$${\epsilon }_{re}=\frac{{\epsilon }_r+1}{2}+\frac{{\epsilon }_r-1}{2}{(1+\frac{10}{u})}^{-ab}$$

Reference

Background for CTL lines: E. Hammerstad and O. Jensen, “Accurate Models for Microstrip Computer-Aided Design”, 1980 IEEE MTT-S International Microwave Symposium Digest. The CTL effective dielectric constant here follows the standard Hammerstad-Jensen microstrip background model, adapted as a quasi-TEM approximation for microstrip-like superconducting control lines.

where $u=W/h$ and the correction terms are:

$$a(u)=1+\frac{1}{49}\ln \frac{u^4+(u/52{)}^2}{u^4+0.432}+\frac{1}{18.7}\ln [1+{\left(\frac{u}{18.1}\right)}^3]$$$$b({\epsilon }_r)=0.564{\left(\frac{{\epsilon }_r-0.9}{{\epsilon }_r+3}\right)}^{0.053}$$

For CTL with W = 1.5 μm, h = 1.2 μm, εᵣ = 4.0 (u = 1.25): εᵣₑ ≈ 2.9596.

5. Characteristic Impedance and Propagation Velocity

$$Z_0=\sqrt{\frac{L}{C}},v=\frac{1}{\sqrt{LC}}$$

6. Propagation Delay

For line length l:

$$T=\frac{l}{v}$$

Display:

Quantity	Formula
Total delay [ps]	T [ps] = (l [m] / v [m/s]) × 10¹²
Delay per μm [ps/μm]	T / l [μm]
Delay per 40 μm [ps/40 μm]	(T / l) × 40

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Model Validity and Warnings

Recommended operating ranges

Condition	Threshold	Meaning
W/h	≥ 10	Wide-line regime; edge effects are small
W/t₁	≥ 10	Conductor is much wider than it is thick
W/λ₁	≥ 10	Width is much larger than penetration depth
t₂/λ₂	≥ 3	Ground plane is sufficiently thick

Validity levels

• High — all four conditions satisfied. Analytical result is expected to be reliable for most design purposes.
• Medium — W/h ≥ 1 but one or more conditions not met. The result is useful as a first-order estimate; field-solver validation is recommended before final layout.
• Low — W/h < 1. The conductor is narrower than the dielectric gap. The parallel-plate assumption breaks down; fringing dominates and the analytical formula is unreliable.

CTL-specific note

For the CTL default (W = 1.5 μm, h = 1.2 μm), W/h = 1.25. This is in the medium validity regime. Strong fringing fields are expected; the result is a first-order estimate and εᵣₑ is computed using an effective dielectric model. EM-solver validation is particularly recommended for CTL if precise delay values are needed.

Validation literature

For measured Nb-process context, see S. K. Tolpygo et al., “Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process With 8 Niobium Layers”, IEEE Transactions on Applied Superconductivity 25(3), 1100905, 2015, and S. K. Tolpygo et al., “Inductance of superconductor integrated circuit features with sizes down to 120 nm”, Superconductor Science and Technology 34(8), 085005, 2021. These papers show where simple stripline / microstrip intuition continues to work and where modern multilayer-process details, vias, ground perforations, and submicron features require calibrated extraction.

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Notes on the Original Spreadsheet

Legacy vs. corrected lower-conductor term

The theoretical formula for line inductance contains the ground-plane penetration term:

$${\lambda }_2\coth \left(\frac{t_2}{{\lambda }_2}\right)$$

The original Excel spreadsheet appears to use h in place of t₂:

$${\lambda }_2\coth \left(\frac{h}{{\lambda }_2}\right)\text{(legacy Excel mode)}$$

For the default process parameters, the numerical difference is very small:

Layer	t₂ (μm)	h (μm)	Δ in L (corrected vs legacy)
BAS	0.3	0.3	0.000 % (t₂ = h)
COU	0.3	0.7	≈ + 0.010 %
CTL	0.3	1.2	≈ + 0.007 %

The reason the difference is so small is that t₂/λ₂ = 3.75 for the defaults, making coth(t₂/λ₂) ≈ 1.000067 ≈ 1. Both coth(t₂/λ₂) and coth(h/λ₂) are extremely close to 1.

Recommendation: use the corrected formula for any process definition where t₂ ≠ h, or where the ground-plane thickness t₂ is less than ~3λ₂.

K factor calibration

The fringing correction factor K was calibrated to reproduce the original spreadsheet outputs for all three default line types to within ±0.03 %. The calibration constants ($a_c=4.226$, $b_c=1.64$) were found by fitting the formula $K=1+a_c(h/W)\tanh (b_c{t}_1/h)$ to the three data points. If you have access to the original Chang (1979) ITED paper or the exact spreadsheet cell formulas, the calculateChangGeometry() function in TransmissionLineCalculator.vue can be updated to reproduce the intermediate variables precisely.

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Regression Reference

These expected outputs are reproduced by the calculator (Legacy Excel mode). Use them to verify that any code changes do not break the numerical results.

BAS — Base-layer stripline

Parameter	Expected
K	≈ 1.2448
L	≈ 0.0968 pH/μm
C	≈ 0.7054 fF/μm
Z₀	≈ 11.72 Ω
v	≈ 1.210 × 10⁸ m/s
Delay (l = 5 μm)	≈ 0.0413 ps
Total L	≈ 0.484 pH
Total C	≈ 0.00353 pF

COU — Counter-layer / coupling line

Parameter	Expected
K	≈ 1.7443
L	≈ 0.2137 pH/μm
C	≈ 0.2559 fF/μm
Z₀	≈ 28.89 Ω
v	≈ 1.352 × 10⁸ m/s
Delay (l = 7.95 μm)	≈ 0.0588 ps
Total L	≈ 1.699 pH
Total C	≈ 0.00203 pF

CTL — Control / microstrip-like line

Parameter	Expected
εᵣₑ	≈ 2.9596
K	≈ 3.0183
L	≈ 0.3775 pH/μm
C	≈ 0.0989 fF/μm
Z₀	≈ 61.79 Ω
v	≈ 1.637 × 10⁸ m/s
Delay (l = 1000 μm)	≈ 6.109 ps
Total L	≈ 377.5 pH
Total C	≈ 0.0989 pF

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Recommended Workflow

A suggested flow for estimating transmission-line parameters for a new process layer:

1. Identify the layer type — is this a buried stripline (BAS/COU style) or a microstrip-like control layer (CTL style)?
2. Enter process geometry — obtain W, h, t₁, t₂ from the process design kit (PDK) design rules.
3. Enter material properties — λ (from published values or wafer measurements) and εᵣ (from the PDK dielectric stack).
4. Select model mode — use "Corrected Chang formula" for new process definitions; use "Legacy Excel" only when reproducing historical data.
5. Check validity — review the W/h, W/t₁, W/λ₁, t₂/λ₂ ratios. If W/h < 2, treat the result as a first-order estimate.
6. Read results — record L [pH/μm], C [fF/μm], Z₀, and delay per μm.
7. Validate with EM solver — for any line used in a critical path (JJ bias, PTL segment, clock driver output), verify with a 2D cross-section EM solver before tapeout.

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Limitations

1. Single-conductor model — does not handle coupled lines, differential pairs, or shielded structures.
2. Uniform cross-section — assumes the cross-section is constant along the line. Effects of bends, vias, or tapers are not modelled.
3. TEM / quasi-TEM only — valid at low frequencies where the transverse dimensions are much smaller than λ_electromagnetic. Not valid for millimetre-wave or sub-THz operation where dispersion is important.
4. Homogeneous ground plane — assumes a single, uniform ground plane. Multi-layer ground structures require a more detailed model or EM simulation.
5. No loss model — quasiparticle loss, surface resistance, and substrate loss are not included. For resonator Q-factor calculations, use a full complex-impedance model.
6. Fringing factor calibration — the K factor is calibrated against three preset data points. For process parameters significantly outside the BAS/COU/CTL range (e.g., W/h > 30 or W/h < 0.5), the result should be treated with additional caution.

Why full extraction becomes necessary

For multilayer layouts with vias, return-current crowding, nearby ground cuts, coupling, bias feeds, and stacked routing, closed-form single-line formulas stop being the controlling model. See C. Fourie, N. Takeuchi, and N. Yoshikawa, “Inductance and Current Distribution Extraction in Nb Multilayer Circuits with Superconductive and Resistive Components”, IEICE Transactions on Electronics E99-C(6), 683-691, 2016, for why full current-distribution extraction is needed in realistic Nb multilayer ICs. For broader tool-chain context, see C. J. Fourie, “Electronic Design Automation tools for superconducting circuits”, Journal of Physics: Conference Series 1590, 012040, 2020.

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Key References

• W. H. Chang, “The inductance of a superconducting strip transmission line”, Journal of Applied Physics 50(12), 8129-8134, 1979. Primary analytical reference for the superconducting stripline inductance model used on this page; most relevant when the line has finite width and $W/h\gtrsim 1$.
• E. Hammerstad and O. Jensen, “Accurate Models for Microstrip Computer-Aided Design”, 1980 IEEE MTT-S International Microwave Symposium Digest. Background reference for the effective dielectric constant used for microstrip-like CTL lines.
• C. Fourie, N. Takeuchi, and N. Yoshikawa, “Inductance and Current Distribution Extraction in Nb Multilayer Circuits with Superconductive and Resistive Components”, IEICE Transactions on Electronics E99-C(6), 683-691, 2016. Best citation for the limits of single-line closed forms in multilayer superconducting layouts with vias, coupling, and realistic return-current paths.
• S. K. Tolpygo et al., “Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process With 8 Niobium Layers”, IEEE Transactions on Applied Superconductivity 25(3), 1100905, 2015. Measured-process validation reference for stripline and microstrip inductance in an advanced multilayer Nb fabrication stack.
• S. K. Tolpygo et al., “Inductance of superconductor integrated circuit features with sizes down to 120 nm”, Superconductor Science and Technology 34(8), 085005, 2021. Advanced reading for modern small-feature superconducting IC inductance, mutual inductance, vias, ground-plane effects, and comparison with extraction tools such as InductEx and wxLC.
• C. J. Fourie, “Electronic Design Automation tools for superconducting circuits”, Journal of Physics: Conference Series 1590, 012040, 2020. Broader overview of superconducting EDA workflows, including physical extraction tools and how they fit into the design flow.

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